基于CPLD的CAN控制器与DSP通信接口设计  

Interface Circuit Design between DSP and CAN Controller Based on CPLD

作　　者：王新平[1] 龚玉梅[1] 王旭辉[1] 

机构地区：[1]中国科学院上海技术物理研究所,上海200083

出　　处：《科学技术与工程》2009年第9期2336-2342,共7页Science Technology and Engineering

基　　金：国家863项目(2006SQ704205)资助

摘　　要：介绍定点DSP处理器TMS320F240和CAN控制器SJA1000的特点,分析各自的接口信号及时序。详细给出基于CPLD的CAN控制器和DSP处理器之间的接口电路的硬件设计方案。提到的设计方法根据CAN控制器的地址和数据线时分复用的时序特点,解决其与DSP的地址线和数据线分离之间所存在的问题。此外,还详细讲述在DSP控制器中使用汇编语言完成SJA1000的初始化、接收和发送CAN总线数据的软件实现。The characteristics of The fixed point DSP processor of TMS320F240 and the CAN controller of SJA1000 are introduced and analyzed the time sequences of the interface signals. The interface circuit design between DSP processor and CAN controller is explained in details, which resolves the problem caused by separation of DSP address bus and the data bus. The methods of using assembly language to initialize the SJA1000, to send and receive the data from the can bus are also introduced in detail.

关 键 词：DSP TMS320F240 CAN总线控制器 CAN接口 

分 类 号：TN914.5[电子电信—通信与信息系统]