一种基于纳米级CMOS工艺的互连线串扰RLC解析模型  

A novel interconnect crosstalk RLC analytic model based on the nanometer CMOS technology

作　　者：朱樟明[1] 钱利波[1] 杨银堂[1] 

机构地区：[1]西安电子科技大学微电子研究所,西安710071

出　　处：《物理学报》2009年第4期2631-2636,共6页Acta Physica Sinica

基　　金：国家杰出青年科学基金(批准号:60725415);国家自然科学基金(批准号:60676009;60776034)资助的课题~~

摘　　要：基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式.基于90和65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统(SOC)的电子设计自动化(EDA)设计和集成电路优化设计.Based on the nanometer CMOS technology,a novel parallel RLC coupling interconnect analytic model is presented.Based on the function approach and reduced order techniques,an analyzable expression for the outlying terminal of the disturbed line is derived by the model in the off-angle step input signal.In the 90nm and 65nm CMOS process,the proposed RLC coupling interconnect analytic model enables to estimate the crosstalk voltage within 4% errors compared with Hspice simulation for various interconnect coupling size.The proposed analytic model can be applied to the design of nanometer SOC and optimizing the design for VLSIs.

关 键 词：纳米级CMOS 互连串扰 分布式 RLC解析模型 

分 类 号：TN43[电子电信—微电子学与固体电子学]