JPEG2000编码系统研究及VLSI实现(英文)  

A Study of JPEG2000 Encoding System and Its VLSI Implementation

作　　者：马涛[1,2] 汶德胜[1] 

机构地区：[1]中国科学院西安光学精密机械研究所,西安710119 [2]中国科学院研究生院,北京100049

出　　处：《光子学报》2009年第4期1011-1019,共9页Acta Photonica Sinica

摘　　要：提出了一种JPEG2000编码系统结构和VLSI方案.该方案以小波子带为单位,多套并行处理.对JPEG2000标准中各个模块的算法进行了逻辑化简、并行编码等优化.如采用双行并行9/7提升小波分解,条带并行的比特平面编码,简化区间更新和并行归一化算术编码等.各模块均以流水线方式工作,其中的比特平面编码和算术编码采用异步流水线方式动态分配执行时间,加速比均接近于流水段数3.以图像信号产生板送入原始图像,编码后送入PC机进行码流截断和解压缩.该系统在各个压缩率下的信噪比与LuraWave商用压缩软件的差距均在0.8dB之内,可见改进后的算法可行且有效,像元时钟可达20MHz.A system architecture and its VLSI implementation for JPEG2000 were presented. Parallel coding architecture based on wavelet sub band was introduced in the system. Simplified logic and parallel processing were adopted to optimize arithmetic for JPEG2000 standard, such as 2-line-parallelling 9/7 lifting discrete wavelet transform, strip paralleling bit plane coding, compacted interval update and parallel renormalization for binary arithmetic coding, etc. All modules are pipelined manner. Especially, asynchronous pipelining implementation was adopted in the BPC and BAC to distribute execution time dynamically. The speed ratio was tested close to pipeline segment 3. Original image is imported by the image data generating board, and the compressed data is send into PC to be truncated and decoded by software. The average difference of PSNR between LuraWave and the proposed system is below 0.8dB, which shows the validity of the improved arithmetic. The input pixel clock can reach to 20MHz.

关 键 词：JPEG2000 离散小波分解 比特平面编码 二进制算术编码 VLSI 异步流水线 

分 类 号：TN919.81[电子电信—通信与信息系统]