基于FPGA的3-DES双向数据传输高速加/解密芯片设计  

Design of FPGA-based 3-DES Two-way High-speed Data Encryption/Decryption Chip

作　　者：石新峰[1] 董蕴华[1] 杨航[1] 

机构地区：[1]河南机电高等专科学校电子通信工程系,河南新乡453002

出　　处：《通信技术》2009年第5期230-232,共3页Communications Technology

摘　　要：介绍了DES和3-DES算法,并阐述了用FPGA芯片进行高速硬件加/解密的设计方法以及关键问题的解决方案,最后利用Altera公司的Cyclone Ⅱ EP2C70F896C8器件设计了一款3-DES双向数据传输加/解密芯片,从而将复杂的加/解密运算通过FPGA单芯片实现,提高了加密速度和破译难度。This paper briefly tells of the DES and 3-DES algorithm, and describes the design and key technologies in using FPGA chips for high-speed hardware encryption/decryption. And with Altera＇s Cyclone Ⅱ EP2C70F896C8 device, a 3-DES two-way data encryption/decryption chip is designed, thus the complex encryption/ decryption operations are realized by the single-chip FPGA, while the encryption speed and the difficulty for cipher-breaking are raised.

关 键 词：DES 3-DES FPGA CYCLONE Ⅱ EP2C70F896C8 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]