基于DDS+PLL频率合成器的设计与实现  

Implementation of frequency synthesizer base on DDS and PLL

作　　者：李俊俊[1] 刘珩[1] 吴丹[1] 

机构地区：[1]中国农业大学信息与电气工程学院,北京100083

出　　处：《电子测量技术》2009年第4期26-30,共5页Electronic Measurement Technology

摘　　要：本文介绍了一种针对某跳频通信系统频率合成器的设计方案。在ADS软件环境下进行设计及仿真,并对结果进行了系统分析。设计方案经测试,该频率合成器可以输出200～270MHz范围内的高精度频率信号,频率步进为25kHz,跳频时间小于200μs,技术指标均达到预期要求。能够满足VHF和UHF波段跳频系统的需求,具有较高的使用价值。An implementation of the frequency synthesizer based on DDS and PLL is described. It is simulated in ADS software and the result is analysised systemly. It is proved that this frequency synthesizer can output 200 MHz to 270 MHz within the scope of high precision frequency signals, which stepping frequency is 25 kHz and lock time is less than 200μs. The frequency synthesizer can meet the needs of the VHF and UHF band frequency hopping system.

关 键 词：直接数字频率合成器 锁相环 压控振荡器 低噪声放大器 低通滤波器 

分 类 号：TN92[电子电信—通信与信息系统]