基于并行处理的EPA通信调度算法研究与实现  

Study and realization of EPA communication schedule algorithm based on parallel processing

作　　者：张先富[1] 冯冬芹[1] 

机构地区：[1]浙江大学控制科学与工程学系工业控制技术国家重点实验室,杭州310027

出　　处：《高技术通讯》2009年第4期434-439,共6页Chinese High Technology Letters

基　　金：国家创新群体基金(NCRGSFC60721062);863计划(2007AA041301)资助项目

摘　　要：针对目前工业以太网(EPA)通信调度算法软件实现方法存在的内存资源耗费多,通信调度表搜索效率低的问题,提出了一种基于现场可编程逻辑门阵列(FPGA)的硬件实现方法。该实现方法采用了一种报文集中存储,通信调度表分别构建的策略,并基于该策略设计了一种并行处理的调度表搜索方法。在以Altera CycloneⅡFPGA为主控芯片的开发平台上的测试结果表明,与软件实现方法相比,该设计方法减少了内存资源的占有率,将报文搜索效率提高了9倍,通信调度性能提高了1倍。In view of the problems of large memory footprint and low lookup efficiency existing in the present software implementation of the EPA （Ethemet for plant automation） communication schedule algorithm, the paper proposes a hardware implementation method based on the field programmable gate array （FPGA）. This method adopts a strategy of storing messages intensively and constructing communication schedule lists separately, and based, on this, devises a parallel processing scheme for lookup of the communication schedule lists. The results of the test on a platform with a Ahera Cyclone Ⅱ FPGA as the main controller show that compared with the software implementation, this implementation method decreases the consumption of memory resources, enhances the message lookup efficiency by 9 times, and doubles the performance of communication.

关 键 词：工业以太网(EPA) 通信调度管理实体 现场可编程逻辑门阵列(FPGA) 通信调度表 并行处理 

分 类 号：TP273.5[自动化与计算机技术—检测技术与自动化装置]