可重构DES、3-DES加减密系统设计  

Design of Reconfigurable System of DES and tri-DES

作　　者：王莉[1,2] 王友仁[2] 

机构地区：[1]南京化工职业技术学院,江苏南京210048 [2]南京航空航天大学,江苏南京210016

出　　处：《计算机测量与控制》2009年第4期751-753,772,共4页Computer Measurement &Control

摘　　要：针对目前密码算法软件实现和ASIC实现的局限性,提出可重构加减密系统设计;在分析DES和3-DES算法原理的基础上,通过减少3-DES的密钥长度,设计新型的3-DES加减密系统;综合新型3-DES加减密系统和DES加减密系统,设计基于可重构硬件的DES、3-DES加减密系统,该系统在xinlinx在Virtex-E系列FPGA上成功实现;实验结果显示,该系统兼有软件实现的灵活性和硬件实现的可靠性、高效性、安全性,硬件资源少,同时可以成功抵制密码攻击,密码分析和线性分析。Aiming at solving the shortcoming of cryptogram algorithm＇s software implementation and ASIC implementation, this paper proposes a reconfigurable cryptography system. This paper reduces the length of key based on the principle of DES and 3-DES in order to design a new-style cryptography system of 3-DES. Synthesizing the new-style cryptography system of 3-DES and cryptography system of DES, this paper designs a reconfigurable cryptography system of DES and 3-DES which is based on reconfigurable hardware. The reconfigurable cryptography system is realized on Virtex-E FPGA. The results prove that the reconfigurable cryptography system has not only the flexibility of software implementation but also has the security, speed of hardware implementation; it also hold less hardware resource

关 键 词：DES 3-DES 可重构 FPGA 

分 类 号：TN431[电子电信—微电子学与固体电子学]