改进型CIC抽取滤波器设计与FPGA实现  

Design of Modified CIC Decimation Filter and FPGA Implementation

作　　者：张杰[1] 戴宇杰[1] 张小兴[1] 吕英杰[1] 

机构地区：[1]南开大学南开大学微电子所,天津300071

出　　处：《现代电子技术》2009年第10期22-24,共3页Modern Electronics Technique

摘　　要：为了改善级联积分梳状(CIC)滤波器通带不平和阻带衰减不足的缺点,给出一种改进型CIC滤波器。该滤波器在采用COSINE滤波器提高阻带特性的基础上,级联了一个SINE滤波器,补偿了其通带衰减。硬件实现时,采用新的多相分解方法结合非递归结构,不仅大大减少了存储单元数量,还使电路结构更加规则。经仿真和FPGA验证,改进型CIC滤波器使用较少硬件,实现了阻带衰减100.3 dB,通带衰减仅为0.0001 dB。A modified Cascaded Integral Comb（CIC） filter which improves the passband and stopband characteristics respect to the CIC filter is presented in this paper. A cascaded SINE filter is introduced after the COSINE one which improves the stopband charac- teristics to compensate the passband drop. Applying the new polyphase decomposition as well as no- recursive structure, this filter not only greatly decreases the amount of memory, but also makes the circuit more regular. Simulation and FPGA verification result indicates that the stonhand attenuation is up to 100. 3 dR and the passband attenuation is only 0. 000 1 dB.

关 键 词：CIC抽取滤波器 COSINE滤波器 SINE滤波器 设计优化 FPGA 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]