基于FPGA的Twofish加/解密芯片设计  

Design of Twofish Encryption/Decryption Chip Based on FPGA

作　　者：李佳[1] 姚明林[2] 

机构地区：[1]唐山学院计算机科学与技术系,唐山063000 [2]唐山学院信息工程系,唐山063000

出　　处：《计算机工程》2009年第9期169-170,173,共3页Computer Engineering

摘　　要：针对安全的数据传输及个人隐私权的保护等问题,研究基于FPGA的改进型Twofish加/解密芯片的设计。采用16组Rijndael-like S-boxes设计Twofish算法,提高算法的安全性,加入伪随机数器决定每回合使用的S-boxes,增加攻击者破解的难度。以Altera公司的Stratix EP1S20验证该芯片的功能,结果证明其能达到高安全性的要求。Aiming at the problems of secure data transformation and private protection, this paper researches the design of improved Twofish encryption/decryption chip based on Field Programmable Gate Array（FPGA）. It uses sixteen Rijndael-like S-boxes to improve the security of Twofish algorithm, and adds a pseudo random number generator to determine the S-box applied in each round, which can enhance the performance to against attacks. The improved chip is realized with FPGA Stratix EPIS20 manufactured by Altera Co., and it is proved that this method can enhance the security of the system.

关 键 词：改进型Twofish算法 加/解密芯片 现场可编程门阵列 伪随机数发生器 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]