基于FPGA＋DSP的嵌入式GPS数字接收机系统设计  

System design of embedded GPS digital receiver based on FPGA+DSP

作　　者：胡锐[1] 薛晓中[1] 孙瑞胜[1] 徐志伟[2] 

机构地区：[1]南京理工大学动力工程学院,南京210094 [2]上海船舶设备研究所,上海200001

出　　处：《中国惯性技术学报》2009年第2期187-190,共4页Journal of Chinese Inertial Technology

基　　金：“863计划”资助项目(2009AA12Z321)

摘　　要：介绍了一种基于FPGA+DSP(高速数字信号处理器+现场可编程逻辑门阵列)模块化的数字嵌入式接收机系统设计。由天线及前端射频模块完成GPS信号的接收、下变频及A/D采样,充分利用FPGA的高速并行处理能力和可灵活编程配置的特点实现接收机的基带相关器和用户接口设计,并结合高速DSP的数字信号处理和丰富的片上外围设备实现接收机的信号处理、导航解算及系统间各部分的无缝连接。系统测试结果说明该数字GPS接收机具有功耗低、体积小、集成度高、工作性能稳定的特点。The paper presents an embedded GPS receiver system based on FPGA＋DSP （field-programmable gate arrays＋digital signal processors）. The GPS signal received by antenna is changed to intermediate frequency and sampled by A/D. Then FPGA, which can process data in parallel and be programmed flexibly, is used in the design of correlation and user interface. DSP is designed to process signal and resolve the navigation data at high speed. System test show that this receiver has the characteristics of low power, small bulk, high integration and stable performance.

关 键 词：嵌入式 GPS数字接收机 数字信号处理器(DSP) 现场可编程逻辑门阵列(FPGA) 系统设计 

分 类 号：U666.1[交通运输工程—船舶及航道工程]