IC设计技术中的IP核互连  

IP Core Interconnection in IC Design Technology

作　　者：李雪东[1] 朱运航[1] 

机构地区：[1]湖南信息职业技术学院信息工程系

出　　处：《电子技术（上海）》2009年第5期53-55,共3页Electronic Technology

摘　　要：随着半导体器件和互连线尺寸的不断缩小,越来越多的关键设计指标--性能、抗扰度等,将受到互连线的严重影响。而在SOC设计过程中,最具特色的是IP核利用技术,随着集成的IP核越来越多,基于片上总线的SOC设计技术带来了一些问题。近几年来,将Internet网络中分层互连的思想引入到SOC设计中IP核的互连上来,提出了全新的集成电路体系结构NOC,NOC从多处理体系结构、消除时钟树以节省资源、实现并行通信等几个方面,展示了优于总线结构的本质和特性,成功地解决了SOC设计中存在的问题。It is well-known fact that there exists many problems With the improvement of semiconductors and the sizes of interconnector. Among the many problems confronted by designers nothing is more significant than the effects of interconnect. IP reuse has become one of the main solution in SOC design. SOC design technology based on bus has some disadvantages, such as poor scalability and lower communication efficiency, etc. In recent years, a new architecture NOC is proposed, in which bus interconnection for chip is replaced by computer network interconnection. And it will overcome the disadvantages of SOC design thoroughly and become a mainstream design technology for the next generation integrated circuit.

关 键 词：集成电路 IP 片上系统 片上总线 片上网络 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN470.597