基于DMA的DSP-Cache优化  

DSP-Cache Optimization based on DMA

作　　者：郭强[1] 张斌[1] 

机构地区：[1]东南大学信息科学与工程学院,江苏南京210096

出　　处：《电气电子教学学报》2009年第2期50-53,共4页Journal of Electrical and Electronic Education

基　　金：国家高技术研究发展计划(863计划)资助项目(No.2007AA01Z330)

摘　　要：数字信号处理器大都采用两级高速缓存结构,为高复杂度算法的实现提供了有力的保证。由于一般片上内存空间不大,对于通信和图像系统较大的数据,需要将数据存在片外,从而导致处理效率很低。本文以TIC6000系列芯片为例,从分析它的Cache结构出发,利用直接存储器存取DMA(Direct Memory Access)设计了一种双缓冲区结构,以减少片内、外存储器之间数据交换的时间,并针对高斯滤波函数加以实现。测试表明这种方法能使硬仿真时所用的CPU周期数与软仿真时相同。Digital signal processor generally has a two-level cache structures to realize high-complexity algorithms efficiently. But it usually has small on-chip memory, compared with the large image data. So the communication and image data have to be stored out of the chip, which leads to poor processing efficiency. This paper took the TI C6000 as an example, and based on the cache structure of this series, introduced a double buffering framework so as to reduce the time for exchanging data between the on-chip and out-chip memory. Then this proposed optimization strategy was applied to implement the Gaussian filter function and test its overall performance. Experiment shows that the performance via soft simulation can reach the optimization as emulating on the DSP board.

关 键 词：TIC6000 CACHE优化 DMA 

分 类 号：TN911[电子电信—通信与信息系统]