基于FPGA的智能点钞机设计与实现  

Design and Implementation of a Smart Banknote Counter Based On FPGA

作　　者：冯济琴[1] 吴敏[2] 王先全[1] 郑方燕[1] 

机构地区：[1]重庆理工大学电子信息与自动化学院,重庆400050 [2]重庆理工大学重庆汽车学院,重庆400050

出　　处：《重庆工学院学报（自然科学版）》2009年第5期94-97,共4页Journal of Chongqing Institute of Technology

基　　金：国家自然科学基金青年基金资助项目(50805150)

摘　　要：针对目前市场上点钞机鉴伪技术普遍存在采样速率低、不能完全采样每张纸币的特征的情况,采用FPGA控制AD转换器多通道动态分析纸币的荧光、纸质、磁性等特征值,设计一种具有鉴伪准确度高的智能点钞机.该点钞机硬件MCU采用PH ILIPS的ARMLPC2138,软件根据特征值模板数据库编制.测试结果表明,该点钞机可使漏辨率和误辨率大大降低.Since the counterfeit banknote detection techniques adopted by banknote counters currently sold on the market have such shortcomings as low sampling rate and incapability of sampling each banknote completely, there are inaccurate counterfeit banknote detection, for instance, missing detection and erroneous detection. In order to greatly decrease the missing detection rate and erroneous detection rate, a smart banknote counter with high counterfeit banknote detection accuracy is designed by adopting FPGA to control the AD converter to sample quickly and process the characteristic values of multi-channel dynamic banknotes, for example, fluorescence, paper quality and magnetism.

关 键 词：点钞机 FPGA 鉴伪 漏辨率 误辨率 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]