一种高吞吐率低成本的AES协处理器设计  

High throughput and low lost AES coprocessor implementation

作　　者：易立华[1] 邹雪城[1] 刘政林[1] 但永平[1] 

机构地区：[1]华中科技大学电子科学与技术系,武汉430074

出　　处：《计算机应用研究》2009年第6期2136-2137,共2页Application Research of Computers

基　　金：国家高技术研究发展计划资助项目(2006AA01Z226);湖北省自然科学基金资助项目(2006ABA080)

摘　　要：设计了一种高吞吐率低成本的AES协处理器。在加解密过程中采用共享技术,S盒采用复合域算法,减少了面积的需求;在轮内设计四级流水结构,有效地缩短关键路径,从而提高了处理器的数据吞吐率;同时在密钥扩展模块内插入寄存器,保证了轮密钥与轮循环的同步。基于VirtexII Pro FPGA芯片(90 nm工艺技术)实现该结构,消耗面积仅约2 118 slices;在最高工作频率189 MHz下,128位加密的数据吞吐率达到1.8 Gbps。与同类设计相比,该处理器吞吐率/资源消耗比值较高。This paper presented a high throughput and low lost AES coprocessor. Reduced area by employing sharing between the encryption and decryption processes , employing composite field Sbox for the SubByte. Improved data throughput by fourstage pipeline in round inner. Inserted registers in key expansion module, assuring synchronization between round and round- key. With an implementation of the this architecture with Virtex II Pro FPGA （90 nm process technology ）, this area optimized consumes 2 118 slices. The speed of this implementation is 1.8 Gbps. Compared to previous similar implementations ,the design achieve high the ratio of throughput/area.

关 键 词：高级加密标准 低成本 吞吐率 密钥扩展 

分 类 号：TN402[电子电信—微电子学与固体电子学]