高速数字电路相位噪声测试研究  

Study on Phase Noise Test of High-Speed Digital ICs

作　　者：蒲璞[1] 崔庆林[1,2] 蒲林[1,2] 

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路国家级重点实验室,重庆400060

出　　处：《微电子学》2009年第3期324-327,共4页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(9140A08020207DZ3401)

摘　　要：对高速数字电路相位噪声测试技术进行了探索。利用直接频谱仪法、鉴相器法、鉴频器法等相位噪声测试方法,通过阻抗匹配等合理的测试设计,开发出测试系统,对高速数字电路相位噪声进行了测试研究,获得了准确的测试数据,有效地表征了电路实际性能。An investigation was made into techniques for testing phase noise of high-speed digital ICs. Using several phase noise test methods, such as direct spectrum analyzer, phase detector and frequency detector methods, a test system was developed, through reasonable test design, such as impedance matching, to study phase noise of high-speed digital ICs, and accurate test data were obtained, which correctly characterize performance of ICs under test.

关 键 词：数字电路 相位噪声 鉴相器 鉴频器 阻抗匹配 

分 类 号：TN707[电子电信—电路与系统] TN79