高速低功耗多模分频器的设计  

A High-Speed and Low-Power Multi-Modulus Divider

作　　者：曾秋玲[1] 蔡竟业[1] 文光俊[1,2] 王永平 

机构地区：[1]电子科技大学通信与信息工程学院RFIC研究室,成都610054 [2]广州润芯信息技术有限公司,广州510663

出　　处：《微电子学》2009年第3期371-375,共5页Microelectronics

摘　　要：基于相位转换技术的多模分频器由于其在工作频率和功耗中能更好地折中而得到广泛的应用。为了进一步降低功耗,利用两级反相器对其相位信号进行整形,使工作频率最高的前两级÷2分频器能降低输出幅度的要求,从而大大降低功耗。这两级反相器还可以调整相位信号占空比为25%,甚至更小,从而增大相位控制信号的延时余量,实现无毛刺的加计数相位转换。基于相位转换4模分频器的基本原理,设计了一个2.55GHz的多模分频器。仿真结果表明,采用0.35μm BiCMOS工艺,在3.3V电源电压下,分频值为128～255,最大功耗不到14mW。Multi-modulus divider （MMD） based on phase-switching technology finds wide application due to good trade-off between operating frequency and power consumption. For lower power consumption, the output amplitude of the first two dividers was reduced by two-stage inverter, which could also adjust duty cycle to 25% or less, thus increasing delay budget in phase control and eliminating glitch completely. Based on the principle of phase-switching four-modulus frequency divider, a multi-modulus divider operating beyond 2. 55 GHz was designed. Simulation results showed that the frequency divider consumed less than 14 mW of power from 3. 3 V supply, while the divider modulus changed from 128 to 255.

关 键 词：分频器 多模分频器 相位转换 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN772