高帧频CCD图像传感器驱动时序设计  

Design for CCD Image Sensor Schedule Generator with High Frame Rate

作　　者：黄磊[1,2] 李自田[2] 孟楠[1,3] 刘美莹[1,2] 

机构地区：[1]中国科学院研究生院,北京100039 [2]中国科学院西安光学精密机械研究所,西安710119 [3]解放军西安通信学院通信指挥系,西安710106

出　　处：《电子器件》2009年第2期262-264,268,共4页Chinese Journal of Electron Devices

基　　金：国家自然基金(保密)资助(60532070)

摘　　要：针对某高帧频CCD可见光相机的设计要求,提出一种可行的驱动时序设计方法。采用Sarnoff公司的VCCD512H面阵CCD传感器,结合多通路数据传输的思路分析了传感器驱动时序关系,以Xilinx公司的FPGA芯片XQ2V3000作为时序发生器并实现数据缓存,从而实现了时序发生器与数据缓存的一体化设计。在Xilinx-ISE9.1i开发环境下采用VHDL语言编程,通过Modelsim SE6.2b实现仿真,结果满足设计要求。Put forward an available method aimed at the requirements of CCD visible light camera with high frame rate. Driving schedules of VCCD512H CCD sensor produced by Sarnoff corporation have been examined. The design takes the FPGA XQ2V3000 which produced by Xilinx corporation as the schedule generator and data cache. Xilinx-ISE9. li has been chosen as the software design platform. Driving schedule generator is described with VHDL. The designed generator has been successfully fulfilled the requirements though simulation by Modelsim SE6.2b.

关 键 词：CCD可见光相机 多路输出 高帧频 FPGA 

分 类 号：N945.23[自然科学总论—系统科学]