2.1GHz射频CMOS混频器设计(英文)  

Design of 2.1 GHz RF CMOS Mixer

作　　者：李恩玲[1] 苑永霞[1] 褚蒙[1] 王雪[1] 

机构地区：[1]西安理工大学理学院,西安710048

出　　处：《电子器件》2009年第2期338-342,346,共6页Chinese Journal of Electron Devices

基　　金：陕西省教育厅专项科研计划项目资助(04JK265)

摘　　要：设计了一个用于第三代移动通信的2.1 GHz CMOS下变频混频器,采用TSMC 0.25μm CMOS工艺。在设计中,用LC振荡回路作电流源实现低电压;并用增大电流和降低跨导的方法提高线性度。在Cadence RF仿真器中对电路进行了模拟,在1.8 V电源电压下,仿真结果为:1 dB压缩点P1 dB-10.65 dBm,IIP3 1.25 dBm,转换增益7 dB,噪声系数10.8 dB,功耗14.4 mW,且输入输出端口实现了良好的阻抗匹配。并用Cadence中的Virtuoso Layout Editor软件绘制了电路的版图。A 2. 1 GHz CMOS down-conversion mixer which is intended for using in 3 G is designed based on TSMC 0. 25 μm CMOS technology. In this design,a LC oscillating circuit is used to realize the low-voltage design of the current source, and the methods of increasing current and decreasing transconductance are used to improve the line- arity. The circuit is simulated in the RF emulator of Cadence under 1.8 V supply voltage, and results of simulation are 1 dB compression point of --10. 65 dBm,IIP3 of 1.25 dBm,the conversion gain of 7 dB, the noise figure of 10. 8 dB,and the power consumption of 14. 4 mW. There is a good impedance matching between input ports and output ports. And,the layout of the mixer is drawn by means of the Virtuoso Layout Editor.

关 键 词：射频集成电路 CMOS混频器 阻抗匹配 线性度 

分 类 号：TN492[电子电信—微电子学与固体电子学]