基于无线传感网络的AES协处理器设计  

AES Coprocessor Implementation Based on Wireless Sensor Network

作　　者：易立华[1] 邹雪城[1] 刘政林[1] 但永平[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《微电子学与计算机》2009年第6期102-104,共3页Microelectronics & Computer

基　　金：国家高技术研究发展计划资助项目(2006AA01Z226);湖北省自然科学基金资助项目(2006ABA080)

摘　　要：无线传感器网络中大部分节点采用电池供电,面积、功耗成为重要的参数.在兼顾速度,功耗情况下设计了一种低成本的AES协处理器.加解密过程中采用复用和共享技术,获得了一个低成本的AES结构,在整个结构中只利用了4个S盒,并采用DSE结构实现S盒,降低了电路功耗.基于Virtex Ⅱ Pro FPGA芯片(90nm工艺技术)实现该结构,消耗面积仅约34k门;在130MHz工作频率下,128位加密的数据吞吐率达到0.67Gb/s.与同类设计相比,该处理器在可接受的吞吐率、功耗下取得了低成本优势,可应用在无线传感网络(WSN)节点芯片中.Area and power is very important parameter in wireless sensor network, because its most node is small in area and powered by limited battery. In this paper we present a low-area AES Co-Processor architecture for wireless sensor network. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of DSE datapath for the SubBytes, which can reduce power consumption. With an implementation of the architecture with Virtex II Pro FPGA （90 nm process technology）, our area optimized consumes 34k equivalent gates. The speed of this implementation is also reduced to 0.67 Gb/s in 130 MHz frequency. Compared to previous similar design, our design achieves significantly low-cost area with acceptable throughput. This architecture can be used in wireless sensor network node chip.

关 键 词：AES 低成本 DSE 密钥扩展 

分 类 号：TN402[电子电信—微电子学与固体电子学]