基于面积的LUT结构FPGA的工艺映射  

Area Based Technology Mapping for Lookup Table Type FPGAs

作　　者：张万鹏[1] 童家榕[1] 唐璞山[1] 

机构地区：[1]复旦大学电子工程系集成电路CAD实验室

出　　处：《微电子学》1998年第3期176-179,共4页Microelectronics

基　　金：国家"九五"重点科技攻关项目

摘　　要：提出了一种基于面积的针对ＬＵＴ结构ＦＰＧＡ的工艺映射算法。该算法在映射的过程中充分利用了网络节点的属性，通过计算节点的参数，采用线性规划方法给出网络的目标函数和约束条件，把一个电路网络的问题转化为纯数学的规划问题求解，映射问题转化为节点属性的分配问题，来得到最后的映射结果。与其它算法相比，该算法的映射结构较优。An area based technology mapping algorithm for lookup table(LUT) type FPGA is presented. The algorithm fully exploits the characteristics of the nodes during the mapping phase and calculates the parameters of the nodes. Linear programming is used to give out the objective functions and the corresponding constraints of the network. A problem of the network is converted to a pure mathematical problem—programming problem to solve, while mapping problem is to allocate the attributes over all the nodes to meet the objective function and constraints. Better results have been achieved, compared to other algorithms.

关 键 词：VLSI ASIC FPGA 工艺映射 设计 

分 类 号：TN470.2[电子电信—微电子学与固体电子学]