10Gb/s 0.18μm CMOS限幅放大器  

10-Gb/s 0.18-μm CMOS Limiting Amplifier

作　　者：吴军[1] 王志功[1] 

机构地区：[1]东南大学射频集成电路与系统教育部工程研究中心,江苏南京210096

出　　处：《中国集成电路》2009年第6期23-25,共3页China lntegrated Circuit

基　　金：国家863计划项目(2007AA01Z2A5)资助

摘　　要：采用SMIC 0.18μm 1P6M混合信号CMOS工艺设计了10Gb/s限幅放大器。该放大器采用了带有级间反馈的三阶有源负反馈放大电路。在不使用无源电感的情况下,得到了足够的带宽以及频率响应平坦度。后仿真结果表明,该电路能够工作在10Gb/s速率上。小信号增益为46.25dB,-3dB带宽为9.16 GHz,最小差分输入电压摆幅为10mV。在50Ω片外负载上输出的摆幅为760mV。该电路采用1.8V电源供电,功耗为183mW。核心面积500μm×250μm。Using SMIC 0.18- μ m 1P6M mixed-signal CMOS process, a 10Gb/s limiting amplifier is realized. Without any inductors, the bandwidth of the amplifier is effectively increased while maintaining a flat frequency response by using a third-order interleaving active feedback. The post-simulation indicates that it can work at the bit-rate of 10Gb/s, and has a small-signal gain of 46.25 dB, a -3-dB bandwidth of 9.16 GHz, and an input sensitivity of 10mV@10Gb/s. It can achieve a output swing of 760 mV when loaded by 50Ω external resistors. The circuit consumes a DC power of 183 mW from a 1.8V supply voltage. The active area is 500 μ m × 250 μ m.

关 键 词：0.18 μm CMOS 限幅放大器 有源负反馈 级间反馈 

分 类 号：TN722[电子电信—电路与系统]