低噪声高速全差分BiCMOS电荷泵锁相环设计  

Design of the low-noise high-speed differential charge-pump phase-lock loop

作　　者：刘鸿雁[1] 栾孝丰[1] 刘传军 

机构地区：[1]中国人民解放军92941部队,辽宁葫芦岛125001 [2]上海意法半导体公司,上海200241

出　　处：《西安电子科技大学学报》2009年第3期557-562,共6页Journal of Xidian University

基　　金：国家教育部博士点基金资助(20010701003)

摘　　要：提出了一种高性能的低噪声高速电荷泵锁相环电路.电路采用全差分结构设计;利用速度快、低功耗的CMOS和电流开关逻辑（CML）电路构成功能单元;提出的差分电荷泵环路滤波器结构明显节省了芯片面积.整个电路采用0.6μm BiCMOS工艺实现,并用Hspice进行仿真验证,结果表明锁相环电路功耗为77 mW,中心频率223 MHz,频率输出范围102~800 MHz,各项性能满足设计指标要求,并使芯片噪声、速度和功耗最优.A high-performance Charge Pump Phase Lock Loop（CPPLL） of low-noise high-speed is presented. The all-differential structure is used in design; Two kinds of high-speed low-power consumption logic circuits--CMOS and Current Mode Logic （CML） are introduced to compose the operation unit; the proposed differential charg-pump loop-filter saves the die area observably. The entire circuit is implemented in the 0.6μm BiCMOS process. Results from HSPICE simulation show that the power dissipation is 77mW, that the center-frequency is 223MHz, and that the frequency range is 102 MHz-800 MHz. The specifications are satisfied and the characteristics such as noise, speed, and power consumption are optimized remarkably.

关 键 词：低噪声 高速 电荷泵 锁相环 

分 类 号：TN433[电子电信—微电子学与固体电子学]