Design and implementation of a DSP with multi-level low power strategies for cochlear implants  

作　　者：麦宋平 Zhang Chun Chao Jun Wang Zhihua 

机构地区：[1]Department of Electronic Engineering, Tsinghua University, Beijing 100084, P.R. China [2]Institute of Microelectronics, Tsinghua University, Beijing 100084, P.R. China

出　　处：《High Technology Letters》2009年第2期141-146,共6页高技术通讯（英文版）

基　　金：Supported by the National Natural Science Foundation of China (No. 60475018)

摘　　要：This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

关 键 词：digital signal processor （DSP） cochlear implant （CI） low power algorithm optimization operand isolation clock gating memory partitioning 

分 类 号：TN64[电子电信—电路与系统]