1.2 GSPS数字信道化接收机的设计与实现  

Design and implementation of a 1.2 GSPS digital channelized receiver

作　　者：王永明[1] 王世练[1] 张尔扬[1] 

机构地区：[1]国防科技大学电子科学与工程学院,湖南长沙410073

出　　处：《系统工程与电子技术》2009年第6期1324-1327,共4页Systems Engineering and Electronics

基　　金：国家部委预研基金项目资助课题(113030401)

摘　　要：在推导实信号数字信道化接收机高效结构的基础上,在硬件平台上完成了1.2 GSPS的16通道数字信道化接收机的实现。在FPGA实现中充分考虑了高速数据的可靠接收以及片内的数字处理速度和资源的优化,保证了系统良好的性能。实际中频测试结果表明,该数字信道化接收机的功能正确,性能稳定。Based on the efficient structure of the real signal digital channelized receiver, a 1.2 GSPS receiver of 16 sub-channels is realized in hardware platform. In FPGA design, reliable receiving of high speed data as well as the processing speed and resource optimizing inside the chip are maturely considered to insure the good performance. The intermediate frequency test results of the receiver verify its correctness and stability.

关 键 词：无线电侦察 接收机 数字信道化 多相滤波 现场可编程门阵列 

分 类 号：TN971[电子电信—信号与信息处理]