应用于5GHz WLAN的单片CMOS频率综合器  

A Monolithic CMOS Frequency Synthesizer Used for 5 GHz Wireless LAN

作　　者：吴秀山[1,2] 王志功[1] 康建颖[1] 马成光[1] 金琳[1] 刘静 李青[2] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096 [2]中国计量学院机电工程学院,杭州310018 [3]山东省质量技术监督干部学校,济南250014

出　　处：《固体电子学研究与进展》2009年第2期231-236,共6页Research & Progress of SSE

基　　金：国家自然科学基金(No.60772008)资助课题

摘　　要：采用中芯国际(SMIC)的0.18μm混合信号与射频1P6MCMOS工艺实现了WLAN802.11a收发机的锁相环型频率综合器,它集成了压控振荡器、双模预分频器、鉴频鉴相器、电荷泵、各种数字计数器、数字寄存器和控制等电路。基于环路的线性模型,对环路参数的优化设计及环路性能进行了深入的讨论。流片后测试结果表明,该频率综合器的锁定范围为4096～4288MHz,在振荡频率为4.154GHz时,偏离中心频率1MHz处的相位噪声可以达到-117dBc/Hz,输出功率约为-3dBm。芯片面积为0.675mm×0.700mm。采用1.8V的电源供电,核心电路功耗约为24mW。A PLL（phase-locked loop） type frequency synthesizer used for WLAN 802.11a has been implemented in the standard 0. 18 μm mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, a PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detail. The measured results show that the locked range was 4096-4288 MHz and the phase noise could reach-117 dBc/Hz at 1 MHz offset from the carrier 4. 154 GHz, the output power is about -3 dB. The chip area is 0. 675 mm×0. 700 ram. The DC power consumption of the core part is about 24 mW under 1.8 V supply.

关 键 词：频率综合器 锁相环 压控振荡器 预分频器 鉴频鉴相器 电荷泵 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]