一个低电压低功耗10位30MS／s流水线A／D转换器  

A High Performance Low Power 10 bit 30 MS/s Pipelined ADC

作　　者：谢磊[1] 李建[1] 曾晓洋[1] 郭亚炜 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]鼎芯通讯上海有限公司,上海201203

出　　处：《固体电子学研究与进展》2009年第2期291-296,共6页Research & Progress of SSE

摘　　要：实现了一个10位精度,30MS/s,1.2V电源电压流水线A/D转换器,通过采用运放共享技术和动态比较器,大大降低了电路的功耗。为了在低电源电压下获得较大的摆幅,设计了一个采用新颖频率补偿方法的两级运放,并深入分析了该运放的频率特性。同时还采用了一个新的偏置电路给运放提供稳定且精确的偏置。在30MHz采样时钟,0.5MHz输入信号下测试,可以得到8.1bit有效位的输出,当输入频率上升到60MHz(四倍奈奎斯特频率)时,仍然有7.9bit有效位。电路积分非线性的最大值为1.98LSB,微分非线性的最大值为0.7LSB。电路采用0.13μmCMOS工艺流片验证,芯片面积为1.12mm2,功耗仅为14.4mW。This paper describes a 10-bit 30-MS/s 1.2 V supply voltage pipelined ADC. The power consumption of the ADC is reduced by using amplifier sharing technique and the dynamic comparator. A two-stage OTA （operational transconduetance amplifer）is analyzed and designed, and a stable high swing bias circuit is used for the wide swing amplifier in low voltage. The ADC exhibits 8.1 bit effective number of bits （ENOB） for 0. 5 MHz input frequency at 30 MS/s, while maintaining 7.9 bit ENOB for input signal up to 60 MHz. The measured integral and differential nonlinearities of the prototype show less than 1.98 least significant bit （LSB） and 0. 7 LSB respectively at 30 MS/s. The ADC was fabricated in a 0. 13 μm CMOS process occupying 1.12 mm^2. The power consumption of the ADC is only 14.4 mW.

关 键 词：模数转换器 流水线 低电压 低功耗 运算放大器 频率补偿 

分 类 号：TN792[电子电信—电路与系统]