锁相频率合成器的噪声优化设计  

Noise Optimization of the PLL Synthesizer

作　　者：段振亮[1] 段红[1] 李钊[2] 孟丁 

机构地区：[1]国防科技大学机电工程与自动化学院,湖南长沙410073 [2]第二炮兵驻石家庄地区军事代表室,河北石家庄050081 [3]第二炮兵驻699厂军事代表室,北京100036

出　　处：《无线电工程》2009年第6期55-57,64,共4页Radio Engineering

摘　　要：简要介绍了锁相环频率合成的原理,对环路内和环路外的噪声进行了详尽分析,提出为了使系统性能达到最优,应该采取哪些措施、选择哪些器件以及怎样设计匹配电路的原则和方法。使用PLL Design&Simulation仿真软件,对环路滤波器在采用有源滤波器和无源滤波器2种情况下鉴相器和VCO的输出信号进行了仿真,从仿真结果可以看出,环路滤波器应尽量选择无源滤波器。This paper introduces the principles of the PLL synthesizer, analyses the noise source of the PLL thoroughly, and puts forward ways of optimizing the system with respect to each kind of noise, including how to choose components and how to design circuits. The paper uses the PLL Design ＆ Simulation software to simulate the output signals of the PD and VCO and the results show that passive filter is quite better than active filter. The passive filter should be selected to minimize the system noise.

关 键 词：锁相环 噪声 仿真 滤波器 

分 类 号：TN742[电子电信—电路与系统]