SDH集成芯片的设计  

The Design of SDH Integrated Chip

作　　者：王瀚晟[1] 张晓如[1] 沙燕萍[1] 皇甫伟[1] 宋浩宇[1] 曾烈光[1] 

机构地区：[1]清华大学

出　　处：《光通信研究》1998年第3期9-13,33,共6页Study on Optical Communications

摘　　要：本文介绍了几种应用于ＳＤＨ的技术，其中包括并行帧同步技术和并行扰码技术。采用这两项技术可以在低速电路上完成以前必须在高速电路上完成的功能，从而提高电路的稳定性，降低功耗。同时还介绍了一种匀滑ＡＵ－４的２４ｂｉｔ指针抖动的数字化预处理方法。另外，文章介绍了通过利用这些技术开发研制的ＳＴＭ－１复接专用集成电路ＴＳＯＨ－９９００－１，并给出了其原理框图。This paper introduces some methods applied in SDH. They include parallel frame aligner and parallel scrambler that can realize the functions that must be realized in high speed circuits before in low speed circuits, so that the circuit's stability is increased and the power dissipation is reduced. And the paper also introduces a digitalization pretreatment method that can smooth the 24 bit jitter caused by AU4 pointer adjustment. In addition, the paper introduces STM1 multiplexing application specific integrated circuit TSOH99001 that uses those methods, and presents the chip's scheme.

关 键 词：并行帧同步 并行扰码 解同步 IC 数字信网 

分 类 号：TN919.34[电子电信—通信与信息系统] TN913.24[电子电信—信息与通信工程]