1.8V 8 bit 200MS/s折叠插值模数转换器设计  

Design of 1.8 V 8 bit 200 MS/s folding and interpolation ADC

作　　者：邹涌[1] 李冬梅[2] 

机构地区：[1]清华大学微纳电子系,北京100084 [2]清华大学电子工程系,北京100084

出　　处：《电子测量技术》2009年第6期27-30,共4页Electronic Measurement Technology

摘　　要：设计了一种8 bit、200MS/s的折叠插值模数转换器。为了提高电路速度,使用分布式采样保持电路处理输入信号,两级折叠电路提高电路的增益和带宽。插值电路使用电流插值,适合低压高速应用。仿真结果显示,在1.8V工作电压、200MHz时钟频率、0.18μm CMOS工艺条件下,差分输入范围0.8Vpp,SNDR为47.6dB,功耗约110mW。An 8 bit,200 MHz folding and interpolating A/D converter is designed in this paper. In order to improve the speed, distributed T/H and two-stage folding are used. Current mode interpolating is realized for the low voltage supply. Based on 0. 18 μm CMCIS technology and 1. 8 V power supply, the A/D converter operates at 0. 8 Vpp and 200 MHz clock frequency. Simulated results indicate that it can achieve SNDR of 47. 6 riB,while dissipating less than 110 mW of power.

关 键 词：分布式采样保持 两级折叠 电流插值 

分 类 号：TN792[电子电信—电路与系统]