IS95/cdma2000授时提取模块的设计  

The design of timing abstraction from IS95/cdma2000 systems

作　　者：王剑[1] 凌翔[1] 

机构地区：[1]电子科技大学通信抗干扰技术国家级重点实验室,成都610054

出　　处：《微计算机信息》2009年第20期249-251,共3页Control & Automation

摘　　要：设计了一种IS95/CDMA2000授时模块,以零中频接收芯片SA9521为核心将射频信号解调到I/Q基带,采用Xilinx公司的Spartan-3A DSP系列FPGA XC3SD1800A进行基带处理,通过接收IS95/CDMA2000前向链路中的导频信道和同步信道,输出高精度秒脉冲和本地时间,秒脉冲精度优于1微秒。A IS95/CDMA2000 timing abstraction module is designed, which shifts radio signal to the I/O baseband through A9521 CMOS chip in Zero-IF architecture. The baseband processes are implemented in Xilinx＇s Spatran-3A DSP FPGA Family-XC3SD1800A. By receiving the PILOT Channel and SYNC Channel in forward link, this module can output second pulses with high precision which is better than 1μs.

关 键 词：IS95 CDMA2000 SA9521 FPGA 授时 

分 类 号：TN402[电子电信—微电子学与固体电子学]