基于AVS标准整数反变换的硬件设计研究  

Research for Hardware Implementation of AVS Integer Inverse Transform

作　　者：林佳亮[1] 王小力[1] 

机构地区：[1]西安交通大学电子与信息工程学院,陕西西安710049

出　　处：《微电子学与计算机》2009年第7期134-137,141,共5页Microelectronics & Computer

基　　金：教育部科学技术重点项目(03151)

摘　　要：对基于AVS标准整数反变换的硬件系统设计进行了研究.系统采用两个子模块A和一个子模块B构成,通过模块复用,实现了流水线结构的一维整数反变换核的运算与设计,明显降低了硬件系统的复杂度.在保证系统运算速度情况下,采用两个一维反变换核和2个32×16的单口SRAM,通过优化控制RAM的地址,完成转置变换,使系统模块在40个时钟周期内可完成一个8×8数据块的变换.在同等速度下与传统设计相比,系统节省面积约60%.A research for hardware implementation of AVS integer inverse transform is introduced in this paper. This system has two sub-modules A and one sub-module B. Using the techniques of module reusing, the pipeline architecture, we can get 1-D integer inverse transform core. This implementation can greatly reduce the hardware complexity. The 2-D integer inverse transform has two 1-D integer inverse transform cores and two single-port SRAM, each of which size is 32 × 16. The whole module can be executed with in 40 clock cycles for processing 8 ×8 data. Compared to conventional architecture, it could save 60% area on the condition of same processing speed.

关 键 词：AVS 整数变换 反变换 模块复用 转置存储器 

分 类 号：TN912.3[电子电信—通信与信息系统]