片上非一致Cache体系结构研究  

A Study of On-Chip Non-Uniform Cache Architectures

作　　者：贾小敏[1] 黄彩霞[2] 张民选[1] 孙彩霞[1] 齐树波[1] 

机构地区：[1]并行与分布处理国家重点实验室,湖南长沙410073 [2]长沙学院计算机科学与技术系,湖南长沙410003

出　　处：《计算机工程与科学》2009年第8期93-98,共6页Computer Engineering & Science

摘　　要：随着集成电路制造工艺的发展,片上集成大容量Cache成为微处理器的发展趋势。然而,互连线延迟所占比例越来越大,成为大容量Cache的性能瓶颈,因此需要新的Cache体系结构来克服这些问题。非一致Cache体系结构通过在Cache内部支持多级延迟和数据块迁移来减少Cache的命中时间,提高性能,从而克服互连线延迟对大容量Cache的限制,已经成为微处理器片上存储结构的研究热点。本文回顾了非一致Cache体系结构模型的研究进展,特别是对片上多核处理器中的非一致Cache体系结构模型进行了详细介绍,比较了不同模型的贡献和不足。最后,对非一致Cache体系结构的发展进行了展望。Large Caches have been adopted as the main components of microprocessors due to the scaling down of the integrated circuits technology. Wire delay has gradually become the performance bottleneck due to its increasing importance in the submicron technology. To accommodate those problems, new cache architectures are required. The Non-Uniform Cache Architectures（NUCA） support multiple access latencies and block migration, thus have the potential capability to reduce hit latency. There have been several different architecture models of NUCA. In this paper, the progress in the architecture models of NUCA is studied, especially the architecture models of NUCA for on-chip multi-processors are described in detail. Then, comparison and discussion of their respective merits and drawbacks are presented. Finally, the future research fields of NUCA architectures are listed.

关 键 词：非一致Cache结构 多级延迟 块迁移 片上多核 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]