一种基于Verilog的弹性分组环调度器的实现  

An implementation of the attemper of RPR based on verilog HDL

作　　者：易欣[1] 张治中[1] 郁智勇[2] 

机构地区：[1]重庆邮电大学通信网与测试技术重点试验室,重庆400065 [2]中兴通讯股份有限公司,深圳518057

出　　处：《光通信技术》2009年第7期42-45,共4页Optical Communication Technology

基　　金：教育部新世纪优秀人才支持计划(NCET_06_0779)资助;中兴通讯股份有限公司基金项目资助

摘　　要：针对弹性分组环公平性算法的工程应用,从算法仿真的角度出发设计了一种基于Verilog实现的算法辅助模块,即调度器模块来模拟现实网络运行,以验证当前算法设计的有效性。理论分析和FPGA仿真结果表明,该调度器可以准确的实现对数据帧和公平帧的拆解、调度和流量产生,具有较高的可行性。In the view of engineering application of RPR fairness algorithm, we put forward an implementation of auxiliary module which was used in the simulation of RPR fairness algorithm by FPGA. This module, which based on Verilog HDL, can emulate the real network to verify the validity of currently designed algo- rithm. Theoretical analysis and FPGA simulation results demonstrate that this attemper can achieve accurate disassembling, scheduling and traffic generation of data frame and fair frame, with high feasibility.

关 键 词：弹性分组环 FPGA 公平性算法 调度原则 

分 类 号：TN913.24[电子电信—通信与信息系统]