双机容错系统中基于FPGA容错控制器的设计  

Design of the Fault_tolerant Controller Based on FPGA in the Dual Fault-tolerant System

作　　者：魏志明[1] 李文新[2] 马动涛[1] 王彬[1] 

机构地区：[1]兰州物理研究所,兰州730000 [2]西北工业大学,西安710072

出　　处：《科学技术与工程》2009年第15期4506-4511,共6页Science Technology and Engineering

摘　　要：根据双机容错系统故障检测和诊断、仲裁技术的常用方案及特点,结合某在研双机容错系统,提出了一种基于FPGA容错控制器的设计方案。仲裁模块作为容错控制器的核心模块,可根据双机工作的监测信号负责完成主备机切换功能。为了实现软硬件心跳故障监控功能,在FPGA内嵌了WTD模块。同时,全局时钟引用于各个模块后,良好消除了输出信号的毛刺问题。实验结果表明,该设计方案满足系统要求,可靠性较好。According to various methods in common use of dual fault-tolerant system and combined with a developing devices, a scheme of the dual faulttolerant controller is proposed based on FPGA. As the core module of the fault_tolerant controller, the arbitrator mechanism is in charge of achieving the switches between the host and the backup machine. Watchdog is designed in FPGA for inpecting heartbeat of sofeware and hardware . And also high eliminating the output signals＇ burrs by using FPGA＇s inner clock signal. The simulational result achieves the command of dual fault-tolerant system and good performance.

关 键 词：双模容错计算机 FPGA 故障检测与诊断 仲裁 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]