JPEG 2000标准中MQ编码器的VLSI结构设计  

VLSI Architecture of MQ Encoder for JPEG 2000

作　　者：尚中祥[1] 宋学瑞[1] 

机构地区：[1]中南大学信息科学与工程学院,湖南长沙410083

出　　处：《现代电子技术》2009年第14期83-86,共4页Modern Electronics Technique

摘　　要：MQ编码器是JPEG 2000标准中重要的无损压缩算法,可获得很高的压缩效率。但因其算法复杂度高,执行速度慢,使其应用受到很大限制。为了获得高速处理能力,设计一种高速MQ编码器的VLSI结构,采用三级流水线结构,对算法进行优化,并改进概率估计表内容。设计使用Verilog进行编程,最后通过Modelsim 6.1进行仿真。实验结果表明,该设计极大地提高了编码速度。这里的研究对于JPEG 2000在实际中的应用有着重要的意义。MQ encoder is an important algorithm of lossless compression in JPEG 2000 ,and it can attain the high efficiency of compression. But it is restricted for its complex algorithm and slow performance. To achieve a high throughput,VLSI architecture of the high speed MQ encoder is designed, which adopts architecture of 3 - stage pipeline and optimizes the algorithm with improving the content of probability estimation table. The design is programmed with Verilog and simulated with Modelsim 6.1. The experimental result shows that the speed of encoder is improved highly. Research of the thesis makes it possible for JPEG 2000 to be used in reality.

关 键 词：JPEG 2000 MQ编码器 VLSI 算术编码 

分 类 号：TN47[电子电信—微电子学与固体电子学]