Statistical Analysis of Full-Chip Leakage Power for 65nm CMOS Node and Beyond  

作　　者：LI Tao YU Zhiping 

机构地区：[1]Institute of Microelectronics, Tsinghua University, Beijing 100085, China

出　　处：《Chinese Journal of Electronics》2009年第1期20-24,共5页电子学报（英文版）

摘　　要：In this paper we address the growing issue of statistical full-chip leakage power analysis for 65nm CMOS node and beyond at the circuit level. Specifically, we first develop a fast approach to analyze the statedependent total leakage power of a large circuit block, considering junction tunneling leakage （Ijunc）, subthreshold leakage （Isub）, and gate oxide leakage （Igate）. We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. The proposed approach is implemented and compared with Monte Carlo simulations on ISCAS85 benchmark circuits and shows high accuracy. Comparison with measurement results of SRAMs is also listed to demonstrate the significance of our method. For a circuit with G gates, the complexity of our approach is o（a）.

关 键 词：Statistical analysis Junction tunneling leakage Gaussian and non-Gaussian parameter distributions 

分 类 号：TP368.3[自动化与计算机技术—计算机系统结构] TN432[自动化与计算机技术—计算机科学与技术]