PDVQ图像压缩芯片的设计与实现  

Design and implementation for partition dynamically vector quantization chip

作　　者：余宁梅[1] 王冬芳[1] 廖裕民[1] 符运强[1] 

机构地区：[1]西安理工大学电子工程系,陕西西安710048

出　　处：《通信学报》2009年第7期91-98,共8页Journal on Communications

基　　金：陕西省自然科学基础研究计划基金资助项目(2006F29);应用材料创新基金资助项目(XA-AM-200714);陕西省教育厅科学计划基金资助项目(08JK380)~~

摘　　要：研制了基于图像块动态划分矢量量化的图像压缩芯片。编码前芯片预测系统可根据图像平滑程度及相邻图像块的空间相关度自动调节待压缩的子图像块尺寸,在保证恢复图像画质的前提下,与恒定图像块尺寸矢量量化相比,图像压缩率平均提高27%,最大提高64%。芯片中码书为256阶16维矢量,并采用方向性分类及码字和值升序排列结构,有效减小了码字搜索范围。芯片的设计与实现基于Charter0.35μm标准CMOS工艺,最终芯片尺寸为2.08mm×2.08mm。测试结果表明,工作电压为3V时,PDVQ图像压缩芯片工作频率可达到100MHz,在该工作条件下芯片功耗为295mW,并可以满足512×512灰度图像在30frame/s下的实时编码要求。Partition dynamically vector quantization （PDVQ） chip was researched and produced to encode images. Before encoding, it first judged the correlation of the encoding image block, and then decided to choose the size of the image blocks. Test result shows that PDVQ chip can improve the compression rate to 27% in average by contrasting with the normal VQ, even to 64%.The size of the codebook in PDVQ chip was 256x16 byte, and all codevectors in the code- book were categorized by direction, in each category codebook codewords were sorted in the ascending order of their sum, this kind codebook architecture could reduce search range largely. The VLSI architecture of PDVQ chip was implemented based on Charter 0.35μm CMOS standard cell technology, its chip area was 2.08mm×2.08mm. Test result shows that, at 3.0V power supply, PDVQ chip can operate up to 100MHz. At this operation,its power dissipation is 295mW, and it can support real-time encoding application for 512×512 gray images at 30fame/s.

关 键 词：信息处理技术 图像编码 矢量量化 CMOS 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]