硬件结构支持的基于同步的高速缓存一致性协议  

Architecture Supported Synchronization-Based Cache Coherence Protocol for Many-Core Processors

作　　者：黄河[1,2] 刘磊[1,2] 宋风龙[1,2] 马啸宇[1,2] 

机构地区：[1]中国科学院计算技术研究所计算机系统结构重点实验室,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《计算机学报》2009年第8期1618-1630,共13页Chinese Journal of Computers

基　　金：国家自然科学基金重点项目(60736012);国家"九七三"重点基础研究发展规划项目基金(2005CB321600)资助~~

摘　　要：共享存储系统中如何高效地实现高速缓存一致性是体系结构设计面临的一个关键问题和难点问题.已有的基于目录的协议存在难于实现、验证复杂和存储空间开销大等问题.面向片上众核处理器,文中提出一种由硬件结构支持、基于同步的高速缓存一致性协议.该方案不使用目录,而是通过使用bloom-filter表示一致性信息,并在并行程序中的同步点维护高速缓存一致性.与现有的基于目录的高速缓存一致性协议相比,该方案可以降低目录协议的实现、验证复杂度.用SPLASH-2测试程序集评估表明,基于同步的协议可以获得与基于目录的协议相当的性能.The efficient support of cache coherence is extremely important to design and implement many-core processors. This paper proposes a synchronization-based coherence protocol to efficiently support cache coherence for shared memory of many-core processors. The unique feature of the scheme is that it doesn＇t use directory at all. Inspired by scope consistency memory model, the protocol maintains coherence at synchronization point. Within critical section, process cores record write sets （which lines have been written in critical sections） with bloom-filter functions. When the core releases the lock, the write set is transferred to a synchronization manager. When another core acquires the same lock, it gets the write set from the synchronization manager and invalidates stale data in its local cache. The scheme is evaluated using programs from SPLASH-2 benchmark. The results show that synchronization-based protocol can achieve similar performance in cost-effective way compared to a directory-based protocol that requires large amount of hardware resources and huge design verification effort.

关 键 词：高速缓存一致性 存储一致性模型 多核处理器 共享存储系统 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]