纳米存储器的多值逻辑设计研究  

Research of Multi-valued Logic Design in Nano-memory

作　　者：周少华[1,2] 熊琦[1] 杨红官[2] 曾云[2] 

机构地区：[1]湖南工程职业技术学院,湖南长沙410151 [2]湖南大学,湖南长沙410015

出　　处：《现代电子技术》2009年第16期167-168,170,共3页Modern Electronics Technique

基　　金：湖南省自然科学基金资助项目(06JJ2085);湖南省教育厅科学研究基金资助项目(07D025;08D042)

摘　　要：为探索解决纳米技术发展的极限问题,讨论纳米技术发展的极限和二值逻辑设计的存储器结构,为应对纳米器件在到硅技术7 nm极限的突破,提出基于二端单电子晶体管的库仑台阶效应的多值逻辑设计的纳米存储器模型,分析9值逻辑逻辑设计的单位纳米存储器的逻辑信号与输出电压之间的关系,发现这样构建的存储矩阵大小几乎成几何级减小,提高了信息密度。In order to explore solutions to limit the development of nano - technology issues,limits of the development of nano - technology and the memory structure of binary logic design are discussed. In response to nano - scale devices in silicon technology to the limit of 7 nm breakthrough,the multi- valued logic design of nano- memory model based on two- terminal single- electron transistor level Coulomb effect is put forward. The relationship between output voltage and logic signal of nano-memory designed by 9 - valued logic design are analysed, size of the storage matrix almost geometric level decreases, the information density is improved.

关 键 词：多值逻辑设计 存储矩阵 几何级减小 信息密度 

分 类 号：TN432[电子电信—微电子学与固体电子学]