基于行列不同插值算法的图像缩放引擎的设计  

Design of Image Scaling Engine Based on Different Interpolation Algorithms in Rows and Columns

作　　者：蔡泽锋[1] 闾晓晨[1] 郑学仁[1] 

机构地区：[1]华南理工大学电子与信息学院微电子学系,广东广州510641

出　　处：《液晶与显示》2009年第4期597-601,共5页Chinese Journal of Liquid Crystals and Displays

摘　　要：为了降低定标器的硬件复杂度并提高液晶显示图像的质量,提出了一种行列采用不同插值算法的图像缩放引擎设计方法。在论述四点三次卷积插值算法和线性插值算法基础上,提出了行列不同计算点数的缩放引擎系统架构。在该架构中,水平缩放采用四点三次卷积插值算法,而垂直缩放采用优化的两点线性插值算法。相比双三次插值算法的实现,减少了9个乘法器的使用,明显节省了实现电路的硬件开销。另外,详细论述了放大单元及相应的滤波器的设计,并将设计结果综合下载到现场可编程门阵列(FPGA)芯片。FPGA验证结果表明,该设计切实可行。This paper presents a design method of image scaling engine based on different interpolation in rows and columns for the hardware complexity reduction of LCD scaler and the image quality improvement of the LCD display. Based on the introduction of 4-points cubic convolution and linear algo-rithm, the system architecture of scaling engine is presented. In this architecture, 4-point cubic convolution algorithm is used in the horizontal interpolation, and 2-point optimized linear algorithm is used in the vertical interpolation. Compared to the design based on Bicubic algorithm, nine multipliers are saved. It is obviously that the hardware complexity is reduced. Then, the scaling unit and corresponding filter is specially recommended. The design is mapped into a FPGA chip, and the FPGA verification results show that the design is feasible.

关 键 词：图像缩放 三次卷积插值 LCD 定标器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]