Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology  

作　　者：姜玉稀 李娇 冉峰 曹家麟 杨殿雄 

机构地区：[1]Microelectronic Research & Development Center,Shanghai University

出　　处：《Journal of Semiconductors》2009年第8期82-89,共8页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.60773081,60777018);the AM Foundation by Science and Technology Commission of Shanghai Municipality(No.087009741000);the SDC Project by Science and Technology Commission of Shanghai Municipality(Nos.08706201800,077062008,08706201000)

摘　　要：Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.

关 键 词：electrostatic discharge gate-grounded NMOS snapback characteristic layout parameters 

分 类 号：TN386.1[电子电信—物理电子学]