可配置宏的快速FPGA布局算法  

Algorithm of Macro-Configurable Fast FPGA Placement

作　　者：徐嘉伟[1] 来金梅[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2009年第16期228-230,共3页Computer Engineering

基　　金：国家自然科学基金资助项目(60776023);国家"863"计划基金资助项目(2007AA01Z285)

摘　　要：提出一种可配置宏模块的快速FPGA布局算法。用解析模型确定所有宏模块及基本逻辑模块的理想位置,通过局部扩散得到一个合理的初始布局方案,用低温模拟退火进一步优化,确定各模块的最终位置。以平方线网总长度为目标函数,与VPR算法相比,该算法能较好地处理宏模块,大大降低布局所耗费的时间,不影响最终布局方案的质量。A fast FPGA placement algorithm which can deal with macro blocks is proposed. It takes advantage of an analytical method to figure out the ideal positions of all the blocks. It adjusts the positions of the blocks by local expansion. The typical simulated annealing algorithm is used to refine the placement at a low temperature. Experimental results show that in comparison with the popular VPR algorithm, the algorithm can deal with macro blocks elegantly and speeds up the placement greatly without deteriorating the quality of final placement.

关 键 词：宏模块 二次规划 快速布局 模拟退火 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]