二维离散小波变换的可重配置VLSI架构  

Reconfigurable VLSI Architecture of 2D-DWT

作　　者：张钒炯[1] 来金梅[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2009年第16期231-233,共3页Computer Engineering

基　　金：国家"863"计划基金资助项目(2007AA01Z285);国家自然科学基金资助项目(60776023)

摘　　要：设计一种二维离散小波变换的可重配置VLSI架构。根据二维图像处理中数据量大、芯片面积主要由片上的SRAM存储器决定的特点,提出使用单口SRAM的内存优化技术,在偶数周期,源数据由片上RAM读出,计算结果存在寄存器组中,在奇数周期,源数据由寄存器组读出,计算结果存放在RAM中。该方法较传统的双口SRAM实现节省了约56%的芯片面积。以此为基础,提出一种改进的基于图像块的扫描方式,使模块之间的数据传输性能相比于通常的基于行的实现方式提高了20%。This paper proposes a reconfigurable VLSI architecture of 2D-DWT. Because of the fact that data amount in 2D image processing is huge and the chip area is dominated by the size of the on-chip SRAM, a memory optimization technique is proposed to use single-port SRAM instead of dual-port SRAM. In even cycles, the source data are read from the on-chip SRAM and stored to register banks after calculation. While in odd cycles, source data are read from register banks and, after calculation, stored to SRAM. The method can save about 56% of the chip area compared to traditional implementations. Based on the new method, the paper proposes an improved block-based scan pattern which makes the data transport verformance between DWT and further-level DWT or tier-1 entropy encoding blocks 20% better.

关 键 词：二维离散小波变换 VLSI实现 可重配置硬件 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]