基于FPGA的CIC滤波器的设计  

Design of Cascade Integrator Comb Filter Based on FPGA

作　　者：谢白玉[1] 杨士中[1] 张承畅[1] 

机构地区：[1]重庆大学通信工程学院,重庆400044

出　　处：《计算机仿真》2009年第8期323-325,共3页Computer Simulation

基　　金：重庆市科委科技创新基金资助项目(8412)

摘　　要：级联积分梳状(CIC)滤波器是一种被广泛应用于软件无线电中实现抽取或者插值的高效滤波器。它主要用于降低或提高采样率,同时也具有低通滤波的作用。CIC滤波器的主要特点是,仅利用加法器、减法器和寄存器(无需乘法运算),占用资源少,实现简单且速度高。针对软件无线电中的多速率信号处理技术,以降低采样率为例,首先简要总结了CIC滤波器的理论要点,重点介绍了基于FPGA的CIC滤波器具体设计方案和实现方法;然后运用VHDL语言在FPGA上进行了仿真、综合,仿真结果验证了设计的有效性和可行性。最后将其成功地运用于DDC芯片的开发中。The Cascaded Integrator Comb filter is an efficient filter widely used for decimation or interpolation in the application of Software Radio. It is mainly used to reduce or improve the sample frequency and can be used as a low pass filter. For the multi - rate signal processing in software radio and in order to reduce sample rate, firstly this paper describes the key points of Cascade Integrator Comb （CIC） filter theory, then a detailed CIC filter＇s design and implementation method based on FPGA are given. Secondly the filter is simulated and synthesized with the FPGA using the VHDL language and its simulation results are given. This result of simulation shows that the design is effective and practical. Finally it is used in the development of circuit of DDC successfully.

关 键 词：级联积分梳状滤波器 现场可编程门阵列 抽取 软件无线电 

分 类 号：TN713[电子电信—电路与系统]