40Gbit/s甚短距离光传输系统发送模块的设计与实现  

Design and implementation of transmitter module in 40Gbit/s very short reach optical transmission system

作　　者：徐捷[1] 胡庆生[1] 许多[1] 苗澎[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《东南大学学报（自然科学版）》2009年第4期656-661,共6页Journal of Southeast University：Natural Science Edition

基　　金：国家高技术研究发展计划(863计划)资助项目(2006AA01Z239)

摘　　要：采用Altera公司的StratixⅡGX FPGA,实现40Gbit/s甚短距离光传输系统发送模块,重点阐述了16∶12转换器芯片的设计.首先基于高速收发器设计高速接口:在接收端采用2种方法实现SFI-5接口的17路数据相位对齐;在发送端由片外时钟驱动发送锁相环,同时增加同步措施,以满足高速收发器时钟管理单元对跨时钟域数据传输的要求,保证收发器的稳定工作.在此基础上,设计出便于后续测试的转换芯片时钟网络.同时设计出基于SDH的帧同步电路、去斜移电路和16∶12映射模块,实现数据从SFI-5接口向VSR-5接口的转换;其中去斜移电路能够动态地去除512bits的斜移量.在SignaltapⅡ下的测试结果验证了时序的正确性,误码率也符合小于10-12的设计指标.Stratix Ⅱ GX FPGA from the Altera Corporation is employed to implement the transmitter module in a 40 Gbit/s very short reach optical transmission system. This paper focuses on the design of 16：12 converter. The high speed interface is designed based on the high speed transceiver： At the receiver, two methods are adopted to align the phase of the 17-channel data; at the transmitter, additional synchronization measure is taken to satisfy the demand from the clock management unit （CMU） to the data transmission between asynchronous clock domains, ensuring the stability of the transceiver. On these bases, the clock network is implemented by considering the reliability and the facility of the follow-up testing. Meantime, a frame aligner based on a synchronous digital hierarchy （SDH） structure, as well as the deskew circuit and the 16：12 mapping module is devised, achieving the conversion of data from SFI-5 interface to VSR-5 interface; the deskew module can eliminate the skew of 512 bits dynamically. The testing results using Signaltap Ⅱ verify the validity of the design. Measured by the Agilent 81250, the error bit rates also meet the design index of being less than 10^-12.

关 键 词：甚短距离 高速收发器 16∶12转换器 帧同步 去斜移 

分 类 号：TN929[电子电信—通信与信息系统]