事务级AHB总线模型研究  

Research of transaction level AHB bus model

作　　者：马秦生[1] 曹阳[1,2] 杨珺[1] 张宁[3] 

机构地区：[1]武汉大学电子信息学院,武汉430079 [2]软件工程国家重点实验室,武汉430072 [3]华硕科技有限公司韧体研发中心,江苏苏州215000

出　　处：《计算机应用研究》2009年第9期3246-3248,共3页Application Research of Computers

基　　金：国家"863"重大专项基金资助项目(2002AA1Z1490);国家教育部博士点基金资助项目(20040486049)

摘　　要：为了克服RTL级AHB总线模型的局限性,提出了采用标准C++扩充的软硬件统一建模语言SystemC构建事务级的AHB总线模型的方法。该方法利用端口来连接模块和通道,利用通道来实现接口中定义的方法。经仿真验证,时序完全符合AHB总线标准,运行速度远高于RTL级下的同类模型。该模型可以有效地克服软硬件协同设计中的时间瓶颈,提高SoC的设计效率,降低设计复杂度,缩短芯片产品的上市时间。In order to deal with the limitations of the AHB bus model on the register transfer level, this paper introduced a method of modeling AHB bus using SystemC at the transaction level. The main idea of this method was that connected the modules to the channels through the ports and implemented the methods in the interfaces through the channels. The experimental results revealed that the bus model is completely compliant to AMBA AHB specification. The rapidity of modeling running un- der the transaction level is higher than that of under the register transfer level The time bottleneck of current hardware/software co-design method can be eased effectively. The efficiency of design SoC and the complexity of design SoC are improved. The time-to-market of chip is reduced.

关 键 词：片上系统 AHB总线 事务级 建模 

分 类 号：TN47[电子电信—微电子学与固体电子学]