基于FPGA的可层叠组合式SoC原型系统设计  

Design of stackable SoC prototyping system based on FPGA

作　　者：姚远[1] 张晓琳[1] 张展[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100190

出　　处：《电子技术应用》2009年第9期65-69,共5页Application of Electronic Technique

摘　　要：为解决单片FPGA无法满足复杂SoC原型验证所需逻辑资源的问题,设计了一种可层叠组合式超大规模SoC验证系统。该系统采用了模块化设计,通过互补连接器和JTAG控制电路,支持最多5个原型模块的层叠组合,最多可提供2 500万门逻辑资源。经本系统验证的地面数字电视多媒体广播基带调制芯片(BHDTMBT1006)已成功流片。Complicated SoC Verification need more logic resource than a Single FPGA provided. Stackable SoC prototyping system based on FPGA was designed to solve the problem. The system adapted module architecture and can support up to five prototyping modules stacked by coupling connectors and JTAG Controller. The maximum resource is 25 million logic-gates. The ASIC of DTMB baseband modulation（BHDTMBT1006） was verified on the SoC prototyping system and successfully taped out.

关 键 词：SoC原型 FPGA系统 验证平台 

分 类 号：TN407[电子电信—微电子学与固体电子学]