高速并行FIR滤波器的FPGA实现  

FPGA implementation of high speed parallel FIR filters

作　　者：张维良[1] 张彧[1] 杨再初[1] 杨知行 

机构地区：[1]清华大学电子工程系微波与数字通信国家重点实验室,北京100084

出　　处：《系统工程与电子技术》2009年第8期1819-1822,共4页Systems Engineering and Electronics

摘　　要：提出了一种基于多相滤波器的并行有限脉冲响应(finite impulse response,FIR)滤波器结构,可以有效提高滤波器运算的吞吐率,与传统的串行滤波器结构比,并行滤波器运算速度可以提高L倍,其中L为并行的路数,并且运算延迟小。首先从理论上分析了基于多相滤波器的并行滤波原理,并以八路并行为例,对FIR滤波运算做了浮点仿真验证。然后用经典符号数表示以及优化定点滤波器系数,并针对滤波器系数设计了流水线结构。最后在Altera的Stratix II系列芯片上实现了定点并行滤波器。可编程逻辑阵列(field programmable gatearray,FPGA)编译以及下载测试结果表明,该滤波器仅占用少量的资源,其等效吞吐率可以达到2 GHz。Based on polyphase decomposition, a novel finite impulse response （FIR） filter structure is proposed, which increases the running speed by L times compared with the serial FIR filter, where L is the number of subfilters, and the parallel FIR filter only introduces very small delay. Firstly the theoretical foundation of parallel FIR filters is analyzed. An example of the floating point parallel 8-channel FIR filter is given to verify the algorithm. Then a fixed point parallel FIR filter is designed, which has optimum canonical signed digits （CSD） coefficients. Each subfilter is also pipelined to increase the running speed. Finally the fixed point parallel FIR filter is implemented in Altera＇s Stratix II field programmable gate array （FPGA）. Compiling and deployment results show that the parallel FIR filters run at the sampling rate up to 2 GHz.

关 键 词：可编程逻辑阵列 有限脉冲响应滤波器 多相滤波器 经典符号数 

分 类 号：TN911.7[电子电信—通信与信息系统]