基于ADF4106和CPLD的频率合成器设计  

Design of Frequency Synthesizer Based on ADF4106 and CPLD

作　　者：张刊[1] 张倩 

机构地区：[1]西安电子工程研究所,陕西西安710100 [2]应用材料(西安)有限公司,陕西西安710119

出　　处：《计算机与网络》2009年第15期40-42,共3页Computer & Network

摘　　要：介绍了锁相环电路的基本构成和原理。以详细框图的形式给出了集成锁相环芯片ADF4106的内部结构,分析了各模块的功能以及相互之间的关系,清楚地描述了该芯片的工作过程和特点。大规模可编程逻辑器件(CPLD)在可编程控制方面有其非常灵活的特点。因此,设计了一个基于ADF4106和CPLD的频率合成电路,CPLD根据外部控制码的要求可以给ADF4106实时的写入频率控制数据,实现对频率点的实时控制。软硬件系统经过测试,输出结果满足指标要求。The basic structure and principle of phase-locked loop circuit are introduced. Detailed block diagrams are given to describe the internal structure of integrated PLL chip ADF4106, the functions of each module and the mutual relationship are analyzed, and the working process of the chip and its characteristics are expressly described. Large-scale complex programmable logic device （CPLD） is very flexible in the programmable control field. Therefore, the frequency synthesizer circuit design which is based on the ADF4106 and CPLD device is forwarded, and in accordance with the requirements of the external control code, frequency control data can be written by CPLD to the ADF4106 in a real-time manner to achieve the real-time control of frequency point. Software and hardware system are tested successively, and the output results meet the index requirements.

关 键 词：锁相环 鉴相 VCO 频率合成 

分 类 号：TN74[电子电信—电路与系统]