一种可配置的Cache/SRAM存储器的设计  

Design of A Configurable Cache/SRAM Memory

作　　者：王敏[1,2] 张铁军[1] 侯朝焕[1] 

机构地区：[1]中国科学院声学研究所,北京100190 [2]中国科学院研究生院,北京100039

出　　处：《微计算机信息》2009年第26期179-181,共3页Control & Automation

摘　　要：不同的应用对存储器结构有不同的需求:在运行控制任务时,需要Cache匹配速度差异;在处理数据流时,需要片内存储器提高访问带宽。本文设计了一种基于SRAM的可配置Cache/SRAM存储器,通过数据存储器独立寻址,控制和数据通路充分共享,实现了一个四路组相连、容量为16KB的Cache和容量为16KB的SRAM。综合结果表明,该设计与普通Cache相比,延时仅增加0.035%,门数增加1.06%。Different applications require different memory architecture for optimal performance and efficiency. For control application the cache should be able to match the speed difference; while for solving date stream, we use the on-chip SRAM to broaden band- width. This paper proposes a configurable Cache/SRAM design based on SRAM. By addressing the data memory independently and sharing hardware between control route and data route, a 4 way-associated 16KB cache and 16KB SRAM is designed. The experiment results show that compared with common cache, the configurable Cache/SRAM only has 0.035% increase of time delay and 1.06% increase of gate count,

关 键 词：可配置 CACHE SRAM 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]